学生对 University of Colorado Boulder 提供的 Hardware Description Languages for FPGA Design 的评价和反馈
课程概述
热门审阅
SK
Oct 27, 2020
I think this is a good start in learning how to write VHDL and Verilog.
I would like to see a next level course or recommendations for further writing code.
AS
May 6, 2020
FIFO assignments in both Verilog and VHDL should define purpose of all the internal nets and registers listed in the problem.
51 - Hardware Description Languages for FPGA Design 的 75 个评论（共 167 个）
创建者 Suhaas N
•Jul 8, 2020
Though the support of this course is quite poor and the forum is really dull, the course in itself is really something!!
创建者 Gregory P
•May 1, 2021
Very good course. lectures, assignments and provided reading material provide a solid foundation for writing HDL code.
创建者 Ayush s
•Jan 16, 2022
good course for getting hands on exposure for learning VHDL and verilog in less time, found it very useful.
创建者 Jinendar K
•Mar 27, 2022
bhut sexy course. mujhe nhi krna ab fir bhi enroll nhi kr paa rha .feeling happy and semd at the same time
创建者 Rei I
•Oct 10, 2021
I've been able to learn pleasantly VHDL and verilog hardware description language I've never experienced.
创建者 19MR12_VENKATESHWARAN K
•Jun 22, 2020
WELL DEFINED EXPLANATION AND VERY GOOD MATERIALS PROVIDED WITH REAL DATA SHEET PROBLEMS TO BE ADDRESSED
创建者 JESUS A R A
•Aug 4, 2020
Nice course but the FIFO wasn't explained clearly in both time but I still completed it with some help
创建者 Jorge V
•Jun 2, 2022
Great course. Very easy to follow. It provides the tools for starting with hdls without effort.
创建者 Akash G
•Aug 30, 2020
amazing experience, great course and handled very easily with the help of two great instructors
创建者 Jakub L
•Jul 8, 2020
Very nice entry level course, teaches the basic concepcts very clearly, overall great.
创建者 Muhammad I
•Jan 11, 2023
Highly recommended this course for those who interested in both VHDL and Verilog
创建者 hyungok t
•Feb 26, 2021
I think that SystemVerilog Design and Verification contents are more required!
创建者 silpa k v
•May 6, 2020
Good description and Way of explaining.
Forums helping out more.
Thankyou.
创建者 EVD17I009 R Y
•Apr 18, 2020
The course is best for beginners and very useful to practice the basics.
创建者 waseem a
•Mar 22, 2020
This course really great and have a lot of fun to learn FPGA Designs.
创建者 Chathura J G
•Jul 7, 2020
Best Course I ever had. Lectures are extremely talented in teaching.
创建者 Phanindra D
•Mar 17, 2020
Great course with in-depth explanations of HDL with Verilog and VHDL
创建者 NATWIJUKA J
•Feb 23, 2024
THIS WAS A VERY GREAT COURSE AS FAR SHAPING My CAREER Is CONCERNED
创建者 Gulbutta O
•Jul 10, 2020
Thanks to the authors for such an interesting and useful course.
创建者 jayavardhan g
•May 5, 2020
it is really fun to learn this course you will really enjoy it,
创建者 Ahmed R M
•Oct 26, 2020
it's very useful course for beginning programming with PFGA
创建者 SALCEDO, N V
•Sep 29, 2020
Great course to explore the comparison of VHDL and Verilog.
创建者 Daniil B
•Jul 28, 2025
I liked that there were multiple programming exercises.
创建者 PAL A R
•Oct 21, 2023
Excellent course with in depth teaching and assignments
创建者 Egar P
•Feb 9, 2022
Amazing course! It helps me understand better about HDL